1. Field of the Invention
The present invention relates to a phase comparator provided in a phase locked loop (referred to as a PLL hereinafter) used for extracting a clock signal that identifies and regenerates a non-return-to-zero (NRZ) receiving signal in a receiving circuit for use in transmitting a digital signal.
2. Description of the Related Art
The following literature are available which describe the conventional techniques relating to the above field.
Publication (1): Dan H. Wolaver, xe2x80x9cPhase-Locked Loop Circuit Designxe2x80x9d, 1991, PTR Prentice Hall, Prentice Hall, Inc., A Paramount Communications Company, Englewood Cliffs, N.J. 07632, P. 222
Publication (2): Vincent von Kaenel, Daniel Aebischer, Christian Piguet and Evert Dijkstra, xe2x80x9cA 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for Microprocessor Clock Generationxe2x80x9d, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 31 [11] (US), 1996, PP. 1715-1722
FIG. 1 shows a structure of a general PLL circuit.
This PLL circuit includes a phase comparator 10 which detects a phase difference between data Si having a phase of xcex8i(t) and an output signal So having a phase of xcex8o(t), and which generates an output voltage Vp proportional to the detected phase difference. A loop filter 30 is connected to an output terminal of the phase comparator 10, and an output terminal of the loop filter 30 is connected to a voltage controlled oscillator (referred to as VCO hereinafter) 32. The loop filter 30 is a circuit which smoothes out the output voltage Vp and extracts a control voltage Vc: proportional to the phase difference. The loop filter includes, for example, a low-pass filter having a resistor R and capacitor C. The VCO 32 is a circuit in which the oscillation frequency is controlled by the control voltage Vc output from the loop filter 30 so as to output the output signal So having the phase of xcex8o. This output signal So is fed back to the phase comparator 10.
In the PLL circuit, the response mode and the response speed are determined by a characteristic of the loop filter 30. In the closed-loop operation of the PLL circuit, in order to seek a stable state (locked state) such that the difference between the phase xcex8i(t) of the input data Si and the phase xcex8o(t) of the output signal So becomes constant (that is, xcex8i(t)xe2x88x92xcex8o(t)=constant), the phase xcex8o(t) of the output signal So automatically approaches that of the output signal Si. If there is no input data Si, the control voltage Vc output from the loop filter 30 is 0, so that the VCO 32 oscillates at a free running frequency fo. When the data Si having the frequency fi is inputted, the phases of the frequency fi and the frequency fo are compared by the phase comparator 10. Then, the output voltage Vp corresponding to the phase difference is inputted to the loop-filter 30 and applied to a control terminal of the VCO 32, so that the phase difference is controlled so as to be a constant value. When the oscillating frequency fo of the VCO is sufficiently close to the frequency fi of the data Si, the frequency fo will be locked to the frequency fi, so that the phase difference becomes constant and there will be no frequency difference.
FIG. 2 is a circuit diagram of the phase comparator described in the publication (1) and shown in FIG. 1.
The comparator includes an input terminal 11 which inputs data Si, and an input terminal 12 which inputs the output signal So from the VCO 32. An inverter 13 which inverts the output signal So is connected to the input terminal 12. Delayed flip-flop circuits (referred to as D-FF hereinbelow) 14 and 15 are connected to the input terminal 11 and the inverter 13, respectively. 2-input exclusive OR gates (referred to as EXOR hereinafter) 16 and 17 are connected to the output sides of the D-FF 14 and 15, respectively.
The D-FF 14 includes a data input terminal D connected to input terminal 11, a clock input terminal CK connected to the input terminal 12, and an output terminal Q outputting the data. The D-FF 14 is a circuit which detects the data Si inputted to the data input terminal D at a positive edge (rising edge) of the output signal So inputted from the clock input terminal CK and stores the inputted data Si. The output terminal Q of the D-FF 14 is connected to one of the input terminals of the EXOR gate 16. The D-FF 15 includes a data input terminal D connected to the output terminal Q of the D-FF 14, a clock input terminal CK which inputs an inverted signal obtained after the output signal So was inverted by the inverter 13, and an output terminal Q outputting the data. The D-FF 15 is a circuit which detects the output signal of the D-FF 14 at a positive edge of the inverted signal of the output signal So inputted to the clock input terminal CK and stores such the output signal of the D-FF 14 . This output terminal Q of the D-FF 15 is connected to one of input terminals of the EXOR gate 17.
The EXOR gate 16 is a circuit which takes the EXOR of the data Si inputted to the two input terminals and the output signal of the D-FF 14, so as to output the output signal S18 from the output terminal 18. The EXOR gate 17 is a circuit which takes the EXOR of the output signal of the D-FF 14 inputted to the two input terminals and the output signal of the D-FF 15, so as to output the output signal S19 from the output terminal 19. The output terminals of the EXOR gates 16 and 17 are connected to the output terminals 18 and 19, respectively.
FIGS. 3A through 3C are timing charts showing the operation of the phase comparator shown in FIG. 2. FIG. 3A is a timing chart where the phase of the data Si matches that of the VCO output signal So. FIG. 3B is a timing chart where the phase of the VCO output signal So is delayed compared to that of the data Si. FIG. 3C is a timing chart where the phase of the VCO output signal So is ahead of that of the data Si. Next, the operation of the phase comparator shown in FIG. 2 will be described with reference to FIGS. 3A-3C.
For example, let us consider a case where the data Si repeat in a sequence of 0, 1, 0, 1, . . .
Referring to FIG. 3A where the phase of the data Si matches that of the VCO output signal So, the output terminals 18 and 19 are outputted by repeating the pulses of the same pulse width (output signals S18 and S19) alternately at the period of the VCO signal So.
Referring to FIG. 3B where the phase of the VCO output signal So is delayed compared to that of the data Si, the output terminal 18 generates a pulse (output signal S18) having a pulse width broader by the phase-delay amount.
Referring to FIG. 3C where the phase of the VCO output signal So is ahead of that of the data Si, the output terminal 18 generates a pulse (output signal S18) having a pulse width narrower by the amount by which the phase is ahead. Thus, the difference between the time average of the output signal S18 and the time average of the output signal S19 becomes a value proportional to the phase difference in the range of xe2x88x92xcfx80 to +xcfx80, so as to carry out the operation of the phase comparator.
Moreover, when the data Si are a sequence of 0, 0, 0, . . . or 1, 1, 1, . . . , the output signals S18 and S19 become 0. Thus, in the case where the data Si having the same repeated values are inputted in a continuous manner as above, the phase comparator outputs biased output signals S18 and S19, so as to be able to prevent jitter in the PLL circuit. In this manner, the phase comparator can be used in the PLL circuit for use in extracting the clock signal that identifies and regenerates the receiving signal from the NRZ-signal data Si.
FIG. 4 shows a conceptual diagram of the conventional charge pump provided at the output side.
This charge pump is a circuit which calculates the time average of the pulses in the output signal S18 and S19 outputted from the output terminals 18 and 19 in the phase comparator shown in FIG. 2, and which charges a capacitor C of the loop filter connected thereto. The charge pump circuit includes input terminals 21 and 22, constant-current sources 23 and 27, switches 24 and 26 such as transistors and the like that operate to switch ON and OFF by the output signals S18 and S19, and an output terminal 25 which outputs the output voltage Vp. The constant-current source 23, switch 24, output terminal 25, switch 26 and constant-current source 27 are connected between the power supply potential Vdd and the ground. Upon supply of the output voltage Vp outputted from the output terminal 25, the loop filter 30 including the resistor R and the capacitor C is charged.
Next, the operation of this charge pump circuit will be described.
The switch 24 switches to ON when the output signal S18 is at xe2x80x9cHxe2x80x9d level, so that the current flows into the loop filter 30 from the constant-current source 23. When the output signal S19 is at xe2x80x9cHxe2x80x9d level, the switch 26 switches to ON, and the current is pulled out of the loop filter 30 by the constant-current source 27. As a result, the output voltage Vp output from the output terminal 25 is smoothed out by the loop filter 30, so that the control voltage Vc is outputted from the output terminal 31 so as to be supplied to the VCO 32.
However, there is the following problem to be solved in the conventional phase comparator 10 (FIG. 1) having the structure shown in FIG. 2 and FIG. 4.
For example, consider a case where the phase of the data Si matches that of the VCO output signal So in the charge pump shown in FIG. 4. Since the output signals S18 and S19 having the same pulse width are outputted alternately from the output terminals 18 and 19 so as to be inputted to the charge pump shown in FIG. 4, an average value of the current supplied to the loop filter 30 becomes 0. However, the control voltage Vc outputted from the loop filter 30 oscillates at Rxc2x7Icp at the period of the VCO output signal So, wherein Icp is the current supplied from the charge pump. The frequency of the output signal So of the VCO 32 thereby fluctuates, so that a problem is caused in that a jitter is generated in the clock signal extracted in the PLL circuit.
Therefore, it is an object of the present invention to provide a phase comparator which overcomes the above drawbacks of the related art.
According to a first aspect of the present invention, a phase comparator comprises: a flip-flop circuit which inputs input data and a clock signal and stores the input data in response to the clock signal; a delay circuit which inputs the input data and delays the input data by a predetermined angle of 0xc2x0-180xc2x0 where a data input of the flip-flop circuit is connected to a data input of the delay circuit; a first logic gate which inputs the input data and an output signal of the flip-flop circuit and which outputs a first output signal by taking an exclusive OR or exclusive NOR of the input data and the flip-flop output signal; and a second logic gate which inputs the input data and an output signal of the delay circuit and which outputs a second output signal by taking an exclusive OR or exclusive NOR of the input data and the delay circuit output signal.
By implementing the above structure, the input data are stored in the flip-flop circuit in response to the clock signal. The first logic gate takes an exclusive OR or exclusive NOR of the input data and the flip-flop outputs signal so as to output the first output signal. On the other hand, the input data are delayed by the delay circuit by a predetermined angle. The second logic gate takes an exclusive OR or exclusive NOR of the input data and the delay circuit output signal so as to output the second output signal.
According to a second aspect of the present invention, there is provided a phase comparator which comprises: a flip-flop circuit which inputs input data, inverted data thereof and a clock signal, and which stores the input data and the inverted data in response to the clock signal; a delay circuit which inputs the input data and the inverted data, and which delays the input data and the inverted data by a predetermined angle of 0xc2x0 through 180xc2x0; a first transfer gate which inputs the input data, the inverted data and an output of the flip-flop circuit, and which transmits an output of the flip-flop circuit when the input data are at a logic xe2x80x9cHxe2x80x9d level; a second transfer gate which inputs the input data, the inverted data and an inverted output of the flip-flop circuit, and which transmits the inverted output of the flip-flop circuit when the input data are at a logic xe2x80x9cLxe2x80x9d level; a first logic inversion circuit which inputs outputs of the first and second transfer gates, and which outputs an first output signal by inverting a summed-up value of two outputs of the first and second transfer gates; a third transfer gate which inputs the input data, inverted data and an output signal of the delay circuit, and which transmits the output signal of the delay circuit when the input data are at a logic xe2x80x9cHxe2x80x9d level; a fourth transfer gate which inputs the input data, the inverted data and an inverted out-put signal of the delay circuit, and which transmits the inverted output: signal of the delay circuit when the input data is at a logic xe2x80x9cLxe2x80x9d level; and a second logic inversion circuit which inputs outputs of the third and fourth transfer gates, and which outputs a second output signal by inverting a summed-up value of the two outputs of the third and fourth transfer gates.
By implementing the above structure, the input data and the inverted data are stored in the flip-flop circuit. When the input data are at a logic xe2x80x9cHxe2x80x9d level, the output signal of the flip-flop circuit is outputted via the first transfer gate. When the input data are at a logic xe2x80x9cLxe2x80x9d level, the output signal of the flip-flop circuit is outputted via the second transfer gate. After the output signals of the first and second transfer gates are summed up, the summed-up output signal is inverted by the first inverter. On the other hand, the input data and the inverted data are delayed by the delay circuit by a predetermined angle. When the input data are at a logic xe2x80x9cHxe2x80x9d level, the output signal of the delay circuit is outputted via the third transfer gate. When the input data are at a logic xe2x80x9cLxe2x80x9d level, the inverted output signal of the delay circuit is outputted via the fourth transfer gate. After the output signals of the third and fourth transfer gates are summed up, the summed-up output signal is inverted by the second inverter.
According to a third aspect of the present invention, in addition to the above first and second aspects of the present invention there is further provided a converter which includes: a third logic gate which inputs the first output signal and the second output signals, and takes exclusive OR or exclusive NOR of the two signals; a first output circuit which inputs the first output signal and an output signal of said third logic gate, and detects whether or not said two signals match, so as to output a phase-delay signal in the event that said two signals match; and a second output circuit which outputs the second output signal and an output signal of said third logic gate, and detects whether or not said two signals match, so as to output a phase-forward signal in the event that said two signals match.
By implementing the above structure, the third logic gate takes an exclusive OR or exclusive NOR of the first output signal and the second output signal outputted from the first logic gate and the second logic gate, respectively (or, outputted from the first logic inversion circuit and the second logic inversion circuit, respectively) according to the above first and second aspects of the invention. The first output circuit detects whether or not the first output signal from the first logic gate and the output signal of the third logic gate match, and outputs the phase-delay signal when the two signals match. The second output circuits detects whether or not the second output signal from the second logic gate and the output signal of the third logic gate match, and outputs the phase-forward signal when the two signals match.
According to a fourth aspect of the present invention, in the above third aspect of the invention each output circuit (of the first output circuit and the second output circuit) includes a logic gate which performs an AND or NAND of data applied at the data input terminals of that output circuit. Thereby, the logic gate takes an AND or NAND of the first output signal and the output signal of the third logic gate, while the logic gate takes an AND or NAND of the second output signal and the output signal of the third logic gate.
According to a fifth aspect of the present invention, in addition to the above first and second aspects of the present invention there is further provided a converter which includes: a first logic circuit, which inverts the first output signal or inverts the inverted first output signal; a second logic circuit, which inverts an output signal of the first logic circuit or inverts the inverted signal so that a phase-delay signal is produced; a third logic circuit which inverts the second output signal or inverts the inverted second output signal; a fourth logic circuit which inverts an output signal of the third logic circuit so that a phase-forward signal is produced; a first switching element which is switched by the first output signal so as to set an output signal of said third logic circuit to a constant potential; and a second switching element which is switched by the second output signal so as to set the first output signal to a constant potential.
By implementing these structures, the first output signal outputted from the first logic gate (or the first logic inversion circuit) according to the first and second aspects of the present invention, is inverted, or this inverted first output signal is inverted. The first output signal outputted from the second logic gate (or the second logic inversion circuit) according to the first and second aspects of the present invention, is inverted, or this inverted first output signal is inverted. For example, when the first output signal is at a xe2x80x9cHxe2x80x9d level, the first switching element is switched ON, so that the output signal of the third logic circuit is set to a constant potential. Moreover, when the second output: signal is at a xe2x80x9cHxe2x80x9d level, the second switch is switched ON, so that the output signal of the first logic circuit is set to a constant potential. The output signal of the first logic circuit is inverted by the second logic circuit or this inverted output signal is inverted, so that the phase-delay signal is outputted. The output signal of the third logic circuit is inverted by the fourth logic circuit or this inverted output signal is inverted, so that the phase-forward signal is outputted.
According to a sixth aspect of the present invention, there is provided a phase locked loop circuit which comprises: a phase comparator which includes: a flip-flop circuit which inputs input data and a clock signal and stores the input data in response to the clock signal; a delay circuit which inputs the input data and delays the input data by a predetermined angle; a first logic gate which inputs the input data and an output signal of the flip-flop circuit and which outputs a first output signal by taking an exclusive OR or exclusive NOR thereof; a second logic gate which inputs the data and the output signal of the delay circuit and which outputs a second output signal by taking an exclusive OR or exclusive NOR thereof; a converter which generates pulses proportional to the phase of the input data and the phase of a voltage controlled oscillator; a charge pump circuit, connected to the converter, which calculates a time average of pulses outputted from the phase comparator; the PLL circuit further comprising: a loop filter, comprised of a resistor and a capacitor and connected to an output side of the charge pump circuit, and which smoothes the output voltage and extracts a control voltage proportional to the phase difference; and the voltage controlled oscillator which controls an oscillation frequency by the control voltage outputted from the loop filter, whereby the output signal is fed back to the comparator so as to serve as the clock signal.
According to a seventh aspect of the present invention, there is provided a phase locked loop circuit which comprises: a phase comparator which includes: a flip-flop circuit which inputs input data, inverted data thereof and a clock signal, and which stores the input data and the inverted data in response to the clock signal; a delay circuit which inputs the input data and the inverted data, and which delays the input data and the inverted data by a predetermined angle of 0xc2x0 through 180xc2x0; a first transfer gate which inputs the input data, the inverted data and an output of said flip-flop circuit, and which transmits an output of said flip-flop circuit when the input data are at a logic xe2x80x9cHxe2x80x9d level; a second transfer gate which inputs the input data, the inverted data and an inverted output of the flip-flop circuit, and which transmits the inverted output of the flip-flop circuit when the input data are at a logic xe2x80x9cLxe2x80x9d level; a first logic inversion circuit which inputs outputs of the first and second transfer gates, and which outputs a first output signal by inverting a summed-up value of two outputs of said first and second transfer gates; a third transfer gate which inputs the input data, inverted data and an output signal of said delay circuit, and which transmits the output signal of said delay circuit when the input data are at a logic xe2x80x9cHxe2x80x9d level; a fourth transfer gate which inputs the input data, the inverted data and an inverted output signal of said delay circuit, and which transmits the inverted output signal of said delay circuit when the input data is at a logic xe2x80x9cLxe2x80x9d level; and a second logic inversion circuit which inputs outputs of said third and fourth transfer gates, and which outputs a second output signal by inverting a summed-up value of the two outputs of said third and fourth transfer gates; a converter, connected to the first logic conversion circuit and the second logic conversion circuit, which generates pulses proportional to the phase of the input data and the phase of a voltage controlled oscillator; and a charge pump circuit, connected to an output side of said converter, which calculates a time average of pulses outputted from the converter; the PLL circuit further comprising: a loop filter, comprised of a resistor and a capacitor and connected to an output side of said charge pump circuit, and which smoothes the output voltage and extracts a control voltage proportional to the phase difference; and the voltage controlled oscillator which controls an oscillation frequency by the control voltage.